46
9140CINDCO02/10
ATA8741
Figure 14-3. External Clock Drive Configuration
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 14-8 on page 46.
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in Reset during such changes in the clock frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. See to System Clock Prescaler on page
47 for details.
Table 14-8. Start-up Times for the External Clock Selection
SUT1..0
Start-up Time from
Power-down and Power-save
Additional Delay from
Reset
Recommended Usage
00
6 CK
14CK
BOD enabled
01
6 CK
14CK + 4 ms
Fast rising power
10
6 CK
14CK + 64 ms
Slowly rising power
11
Reserved
XTERNAL
CLOCK
SIGNAL
CLKI
GND
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